In the semiconductor technology integrated circuit semiconductor devices are becoming increasingly more complex and microminiaturized. As the number of circuits on the device is increased there is a need for more I/O terminals. As the circuit density of the semiconductor device increases there is less space per I/O terminal on the device. Consequently, integrated circuit devices have more terminals, which are smaller in size. Presently devices have been produced which have over 100 I/O pads in the area of approximately 1/4th square inch. Ultimately up to 600 I/O pads may be needed on a single device.
Such I/O terminal density on semiconductor devices presents formidable problems in semiconductor packaging technology. Flip-chip bonding techniques have the potential for forming the electrical connection between the device I/O pads and the corresponding pads on the supporting substrates at great pad densities. However, forming a fan-out electrical connection between the device terminal pads on the substrate and the substrate I/O terminals to the supporting board presents problems. The conventional single layer fan-out printed circuit pattern on substrate surfaces cannot be formed in the very small space provided to accomplish the de-densification of the substrate circuitry. One known technique for forming this necessary fan-out connection structure is using multi-layer ceramic technology. In this technology a plurality of green ceramic sheets are formed, holes punched, the holes filled with a conductive material, circuitry printed on the sheets, and the sheets assembled and sintered. In this manner the fan-out pattern is achieved by bringing it down into the substrate and dispersing it at various levels. However, this is a very complex and expensive technology.
Another technique is forming a plurality of metallurgy layers on the surface of the substrate where each layer is separated by a layer of dielectric material. However, this technique is limited since the lines very closely spaced in a vertical direction. Signals from various lines are induced into the adjacent lines during operation causing errors. Also, the area on the substrate package that is available to I/O pins or other type connections is limited.
Another potential solution to the de-densification problem in the packaging technology presented by a high density device is providing an intermediate element associated with the device that incorporates its own fan-out pattern arrangement of conductors.
This invention is related to this particular solution. In the fabrication of such a intermediate device mounting element very small wires must be accurately positioned and held during their encapsulation with a suitable dielectric material. In view of the very small size of the wires suitable for use in such elements, and the extreme precision required for positioning the wires no suitable apparatus was available prior to this invention for achieving this objective.